Several techniques have been developed in the past for electrically interconnecting various integrated circuit (IC) components. For example, IC chips have been connected to leadframes, package housings, or substrates such as printed circuit boards (PCB's), using such techniques as wire bonding, Tape Automated Bonding (TAB) and solder bumps. These and other prior art interconnects have limitations or disadvantages which are overcome by the present invention. The following background describes these prior art interconnects in order to provide a better understanding of some of the improvements resulting from the present invention.
Wire bonding is by far the most widely used technique for interconnecting silicon devices. For low lead count integrated circuits (less than 100 I/O's), bond pads located on the periphery of the chip rarely influence the dimensions of the thin silicon slab. However, integrated circuits requiring more I/O's often have their exterior dimensions determined not by the active circuitry embedded in the silicon, but rather, by the number of bond pads required to make contact to the leadframe, package housing, or substrate.
Typically, for an IC having a certain lead pitch, there is a minimum chip size required to provide a given number of I/O's. Often the active electronic structures contained within the silicon require dimensions considerably smaller than those dictated by the I/O requirements. As a result, the integrated circuit must be fabricated to a size larger than required by the active electronic structures. This reduces the number of chips per wafer and, therefore, increases the cost per die.
To overcome this problem for high lead count devices, TAB and solder bump interconnects are often used. TAB interconnects can presently be configured at a pitch of four mils, which reduces the effective chip size for interconnection by approximately one-half (two mil pads and two mil spaces) when compared with wire bonding.
Solder bumps, which provide direct interconnection from IC's to substrates or packages, can be located anywhere within the silicon surface. This geometry permits fabrication in a so-called area format, which provides the maximum number of I/O's for a given chip edge dimension. Recently, TAB has also been fabricated in an area format. However, in both cases nonstandard (other than aluminum) metallization is required on the bond pads.
Inasmuch as both TAB and solder bumps require complex chip processing and custom interconnects (leadframes and/or substrates), their use to date has been confined to specialized applications. Therefore, neither of these techniques has replaced use of wire bonds for interconnecting high lead count silicon devices to various components such as substrates or packages.
Thus, the prior art has provided a number of techniques for forming electrical interconnects, but all have limitations or disadvantages.